1. Field of the Invention
The present invention relates to the manufacture of semiconductor devices and, more particularly, to forming a bipolar transistor in a semiconductor material.
2. Description of the Related Art
Presently, the trend in semiconductor technology is toward very large scale integration of devices with high speed and low power dissipation. One such device is the bipolar transistor. In order to achieve high speed in combination with low power, it is essential that the bipolar transistor be made as small as possible. The bipolar transistor may be reduced in size by making the vertical junction structure shallower and reducing horizontal geometry within a given lithographic constraint. However, many of the conventional lithographic processes used to define critical structures in the bipolar transistor become significantly more critical as the horizontal geometries are reduced. Such factors as misalignment and surface non-planarity have substantial adverse impact on the ability of many of the conventional photolithographic techniques to adequately resolve surface structures critically important for the successful fabrication of the high speed, low power bipolar transistors.
For high speed bipolar transistors, the two dimensions of critical importance are the emitter stripe width and the base thickness. The emitter stripe width is defined by the lateral dimension of the emitter region, while the base thickness is defined by the vertical dimension of the base region. The base resistance is directly related to the base thickness and is a major factor in the speed of the transistor. In order to produce bipolar transistors that are both high speed and low power, both the emitter stripe width and the base thickness must be made as small as possible. In this manner the transistor speed is commensurably increased.
In the manufacturing of the bipolar transistor, an emitter window (which defines the emitter stripe width) is located and sized by the use of conventional methods of photolithography masking techniques. Unfortunately, the use of these conventional methods of photolithography masking techniques results in inaccuracies due to, for example, improper alignment of the emitter window with the intrinsic base region. This misalignment results in poor reproducibility and low fabrication yields due to, for example, low emitter to base breakdown voltages.
Various conventional techniques have been used to reduce the problems inherently associated with use of conventional photolithography to form bipolar transistors. One such technique allows the formation of an epitaxial base bipolar transistor using self-aligned polysilicon base contacts. This technique is very desirable since it allows self registration of the emitter implant to the extrinsic base and allows the base contact to be moved from the device base area onto the polysilicon. This self registration reduces the device base area as well as allows control of the distance between the emitter and extrinsic base region. Control of the distance between the emitter and the extrinsic base region of the epitaxial base bipolar transistor is critical. If the distance between the emitter and the extrinsic base, for example, is too narrow then unacceptably low emitter-base breakdown voltages will result.
Many conventional methods of fabricating a self-aligned bipolar transistor depend upon photolithographic methods which require the work surface to be substantially planar. These same conventional methods must then rely on costly and complicated photolithographic and fabrication techniques for producing isolation structures that leave the working surface of the wafer substantially planar. By way of example, U.S. Pat. No. 5,340,753, and U.S. Pat. No. 5,235,206 each use a complicated process to form a plurality of isolation trenches capable of both adequately isolating the transistor and preserving the planarity of the wafer surface for critical photolithographic operations.
While the emitter and base as described above are self-aligned, the process steps are numerous and complicated. In addition, the emitter is defined by conventional photolithographic techniques and therefore, the width of the emitter is limited in size. Additionally, the number and complexity of the above described process renders the manufacture of the bipolar transistor expensive and difficult to control which makes the transistor integrated circuit prone to yield loss. In addition, the process described requires the surface of the device to be planar before the epitaxial base and self-aligned emitter are processed. This additional requirement unnecessarily adds to the fabrication process and precludes the use of highly desirable isolation processes such as LOCOS (Local Oxidation of Silicon).
It is therefore desirable to have a process and an apparatus for efficiently fabricating a high speed, low power epitaxial base bipolar transistor that does not rely on critical lithographic steps. The process should be capable of precisely controlling the emitter to extrinsic base distance in a production environment thereby ensuring consistently high fabrication yields.